An SOI substrate is known as a semiconductor substrate in which an insulating film (an oxide film in many cases) is formed on a substrate and a semiconductor layer (a silicon layer) is formed on it. In a MOSFET to which such an SOI substrate is applied, because the insulating film is formed under a source region and a drain region, a parasitic capacitance can be made smaller compared with a case of a usual bulk substrate in which the SOI layer is not used. As a result, the SOI substrate is superior in high speed operation of the device and it has been widely used.
Generally, the MOSFETs using the SOI substrate is grouped into a fully depleted SOI-MOSFET in which the SOI layer below the gate is depleted and a partially depleted SOI-MOSFET in which the SOI layer is not fully depleted so that a neutral region is left. The partially depleted SOI-MOSFET has an advantage that it can be manufactured by a manufacturing method in which a process for a bulk substrate is used. However, because the neutral region which is electrically separated from the substrate is left, the potential of the neutral region changes depending on an operation condition and operation current changes, namely, so-called floating body effect is caused. For this reason, circuit design becomes difficult.
On the other hand, because there is not an neutral region in the fully depleted SOI-MOSFET, the potential under the channel does not change and there is an advantage that the circuit operation is stable.. However, in the full depleted transistor, unless the SOI layer is made extremely thin, the characteristic degradation of the device is easy to be caused due to punch-through and short channel effects, compared with the partially depleted SOI transistor.
A measure to the characteristic degradation is proposed in which Halo regions where a channel impurity concentration is high are formed on both sides of the channel region. Such a conventional technique is known in Japanese Laid Open Patent Application (JP-A-Heisei 9-293871). FIGS. 1 and 2 show such a semiconductor device.
Referring to FIG. 1, SD (source and drain) regions 103 are formed in the SOI substrate in which a buried insulating film 102 of an oxide film is formed on a base substrate 101 of silicon and a semiconductor layer is formed on the buried insulating film 102. A low concentration region 104 for a channel region and the Halo implantation regions 105 are formed in the region, and a gate insulating film 106, a gate electrode 107, side wall insulating films 108 are formed. Especially, the Halo implantation region 105 has an impurity density profile of the shape shown in FIG. 2 in a lateral direction. The setting of the Halo region with such a high impurity density profile is excellent to restrain the floating body effect.
The profile N(x) of the Halo region 105 of such a conventional semiconductor device in the lateral direction is expressed by the following equation.N(x) =N0+NB0·|exp(−[η·(x−L/2]g)+exp(−[η·(x+L/2]g)|When η is in a range from 8 to 20 or the concentration inclination in the lateral direction is in 3−8×1022 cm−4, the current gain hfe of a parasitic bipolar transistor formed by the SD regions 103 and the low concentration region 104 can be reduced. In addition to the restraint of the short channel effect, the fine and stable operation becomes possible.
However, in the above-mentioned conventional example, the spreading of the impurity distribution from the peak into the lateral direction is about 0.1 μm. When a device is formed to have a gate length of a sub half micron range, the tails of the impurity profiles from both sides overlap and the Halo structure cannot be formed to have high concentration regions on both sides.
If the tails of the impurity profiles from both sides overlap, the impurity concentration in the center portion of the channel region rises, so that the partially depleted SOI-MOSFET operation is easy to be carried out. That is, the fully depleted MOSFET operation becomes difficult. It is demanded that the technique which restrains the floating body effect is established and the technique is different from the conventional method of setting a concentration inclination (a range of η from 8 to 20 or the concentration inclination in the lateral direction is 3−8×1022 cm−4) in accordance with the principle of the conventional example.
Conventionally, the SOI-MOSFETs having various Halo regions are proposed. However, they does not described the effective knowledge to form ideal impurity distribution nor suggests what impurity distribution is proper. Because the gate oxide film becomes thin if the miniaturization of the transistor proceeds, the channel impurity concentration increases to get a necessary threshold voltage. With the increase, the minimum potential decreases so that it is easy to carry out the partially depleted SOI-MOSFET operation. In case of the N-channel transistor, the minimum potential decreases, in case of the P-channel transistor, the maximum potential increases. Thus, the same problem is caused in the N-channel transistor and the P-channel transistor. Hereinafter, the N-channel transistor will be described in this description as long as special notation is necessary. However, it could be understood to the person in the art that the same thing can be applied to the P-channel transistor. In the channel concentration in which the fully depleted MOSFET operation is carried out, it is known that the threshold voltage decreases, and a measure to it is needed.
In conjunction with the above description, an SOI transistor is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-45919). In this conventional example, the transistor is composed of a semiconductor substrate, a buried insulating layer formed on the semiconductor substrate, a semiconductor layer section, a gate insulating film, a gate electrode layer, and a channel region. The semiconductor layer section is arranged on the buried insulating layer and is composed of a top surface, a bottom surface contacting the buried insulating layer, a source region and a drain region. The gate insulating layer is arranged on the top surface of the semiconductor layer section between the source region and the drain region. The gate electrode layer is arranged on the gate insulating layer. The channel region is arranged on the buried insulating layer under the gate insulating layer and is arranged at the semiconductor layer section between the source region and the drain region. The channel region has a top dopant concentration in correspondence to the top surface of the semiconductor layer section, and a bottom dopant concentration in correspondence to the bottom surface of the semiconductor layer section. Here, the top dopant concentration is higher than the bottom dopant concentration.
Also, a silicon semiconductor transistor having a Halo implantation region is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-4198). In this conventional example, the transistor is composed of an insulating layer, and a semiconductor mesa which includes a first surface in contact with the insulating layer and a second surface opposite to the first surface. The semiconductor mesa is composed of a first source/drain region of a first conductive type, a second source/drain region of the first conductive type, a body region, and an implantation region. The body region has a first dopant level of a second conductive type, contacts the insulating layer, extends to the second surface of the mesa and is arranged between the first source/drain region and the second source/drain region. The implantation region is arranged between the first source/drain region and the body region to separate the first source/drain region from the body region. Also, the implantation region is of a second conductive type and has a dopant level which is substantively equal to or higher than the first dopant level.
Also, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-204783. In this conventional example, in the semiconductor device includes a MIS-type electric field effect-type transistor. A region where halogen elements or halogen ions such as fluorine and chlorine exist is provided in at least one of a surface region and an inside region of the active region of the MIS-type electric field effect-type transistor of the semiconductor substrate.
Also, a field effect transistor is disclosed in Japanese Laid Open Patent Application (JP-P 2000-349295). In this conventional example, the field effect transistor is composed of a semiconductor layer, a gate electrode, a source region and a drain region of a first conductive type. An element formation semiconductor layer is covered with an insulator at the bottom at least. A gate electrode is provided on the gate insulating film which is formed on the semiconductor layer. The source region and the drain region of the first conductive type are formed in the semiconductor layer on both sides of the gate electrode. A position where the second conductive type impurity concentration is maximum in the semiconductor layer under the gate electrode is nearer to the semiconductor layer surface than a maximum depth of an inverted layer in the neighborhood of the semiconductor layer surface when the gate electrode is supplied with a voltage larger than a threshold voltage. Also, the second conductive type impurity concentration is monotonously decreased from the maximum depth of the inverted layer toward a boundary between the semiconductor layer and the insulator.